A technique for forming a conductive via in a semiconductor substrate used in a semiconductor device and electrically connecting the upper and under sides of the semiconductor device by the use of the conductive via is known. For example, such a semiconductor device is used in plurality for fabricating an apparatus having a stacked structure in which they are stacked and in which they are electrically connected to one another. For example, the following method is known as a method for forming a conductive via in a semiconductor substrate. A wiring layer is formed on an upper side of a semiconductor substrate. After that, a via hole is made in the semiconductor substrate and the via hole is filled in with a conductive material.
Japanese Laid-open Patent Publication No. 2009-016773
Japanese Laid-open Patent Publication No. 2009-064820
When a semiconductor device in which conductive vias are formed in a semiconductor substrate is fabricated, the conductive vias are formed in the semiconductor substrate in addition to elements, such as transistors. As a result, a fabrication process may become complex. Furthermore, if the conductive vias are formed in the semiconductor substrate, for example, after the formation of a wiring layer, then it may be impossible from the viewpoint of a fabrication process to form the conductive vias with accuracy. Alternatively, there may be need for determining the arrangement of wirings and the like in the wiring layer with the arrangement of the conductive vias taken into consideration.